Job Description

Job Summary/Basic Function:
Semiconductor Microelectronics Assurance, Resilience, and Trust (SMART) Cybersecurity Research invites applications for postdoctoral positions in the general areas of Secure and Trusted Digital Microelectronic and Embedded Systems. The ATM lab is currently being sponsored by the AFRL ADMETE fund (nearly $30M). For more information, please visit: https://webapp2.wright.edu/web1/newsroom/2023/01/12/digital-microelectronics-lab-provides-wright-state-students-with-cybersecurity-training-space/

This position is currently open for Research Assistant Professors interested in conducting research in these areas. Specifically, we are looking for self-motivated candidates with a Ph.D. in Computer Science or Computer Engineering with a strong research background in or related to one or more of the following areas: – Lightweight and Reliable Hardware-based Primitives for Authentication and Cryptography (PUFs, TRNGs, Quantum PUFs, etc.) – Resilient Circuit Designs against invasive and Supply Chain Attacks -Embedded Systems Security (Microprocessors, Microcontrollers, Memory Devices, etc.) – Novel Approaches Against Invasive and Non-Invasive Hardware Attacks: Anti-tampering, Anti-cloning and design overbuilding, Anti-counterfeits, IP/IC Piracy, Anti reverse Engineering, etc. – Secure and Trusted COTS and System-on-Chip Components – Robust Built-in Self Testing and Verification – ML/AI-assisted Mechanisms for Hardware Security and Trust – AI/ML-assisted Hardware Security – Hardware Trojan Detection and Prevention – Hardware-assisted Post-quantum Cryptography – Novel Zero Trust Architectures for Assured Microcontrollers – Novel Approaches to Countermeasure against Malicious Hardware Modification: Fault injections, and Side Channel and Power Analysis Attacks, etc.
Minimum Qualifications
Have a Ph.D. in STEM by the start date.
Demonstrated readiness to write examples and test cases in assembly and HDL languages.
Be familiar with digital design, computer architecture, SoC, VHDL, Verilog, and other CAD tools for security and assurance and formal verification for hardware vulnerability analysis/testing.
Demonstrate proficiency in creating high-level language programs, i.e., Python for ML algorithms.
Show a thorough understanding of digital design and computer architecture concepts and tradeoffs.
Exhibit a solid background in computer security concepts, trends, and recent developments.
Prove proficiency in understanding, designing, and implementing complex combinational and sequential logic for digital circuits.
Preferred Qualifications
Good communication skills, exhibit the ability to perform multiple tasks, and work cooperatively in a team environment.
Have documented the ability or potential to contribute to hardware security and assurance CAD tools, as evidenced by a history of publications or contributions on specific projects, products, tools, and websites.
Have documented the ability or potential to contribute to academic scholarship, evidenced by a history of scientific publications, grant submissions, and conference presentations.
Ability to help mentor graduate/undergraduate students and write and submit research papers in high-impact conferences and journals (IEEE, ACM, Elsevier, Springer, IEEE HoST, IEEE/ACM DAC, IEEE ISACS, etc.)
Have good hands-on experience in hardware security design with FPGA/ASICs, microprocessors/microcontrollers, and memory devices.
Ability to help extend some existing research for building novel secure hardware and make it ready for, available to, and usable by other interested parties. For example, CSE faculty members have designed and simulated a novel 36-bit CPU using synchronous static random-access memory (SRAM) technology and trivial glue logic integrated circuits as components. The candidate may extend this research and address concerns about any possibility of backdoors or maliciously introduced, exploitable defects in computers that may be built using SRAM technology.
Essential Functions and percent of time:
70% of the time will be spent developing research proposals, proposing new security and trust solutions/designs, writing/submitting papers, writing/submitting proposals and helping and supervising UG/G students in their project and experiment. This includes leading a research project in close collaboration with the PI and other lab members, Advance technical aspects of experimental approaches and mechanistic understanding/solving of hardware security and trust challenges.

30% of the time will be spent on teaching the UG/G students and lab management. Providing demonstrations and supervising experiments and investigations. The the candidate shall also be responsible for soliciting and being awarded the grant for the project’s needs beyond 2023.
Essential Functions and percent of time (cont'd):
Non-Essential Functions and percent of time:
Working Conditions
This is a grant funded position with continuation dependent on funding. Special contract terms and conditions of employment apply.

Wright State University, an equal opportunity/affirmative action employer, is committed to an inclusive environment and strongly encourages applications from minorities, females, veterans and individuals with disabilities.

To preserve the safety and security of the campus community and to maintain the integrity of university operations, it is the policy of Wright State University before making an employment offer conduct various background checks, such as a criminal record, credit history when job related and/or education verifications. Additionally, an administrative review shall be conducted whenever the university learns that an employee is charged with or convicted of a crime (except for minor vehicle violations). Frequently asked questions related to background checks may be found on the Human resources website at http://www.wright.edu/human-resources.